Improvements in Integrated Circuit (IC) performance induced the development of Copper (Cu) and low-K dielectrics. Low-K dielectric materials have a small dielectric constant relative to silicone dioxide (SiO2).
Low-K dielectrics supports higher circuit speed enabling smaller feature sizes by increasing the insulation capability around Copper interconnects. The introduction of Cu low-K dielectric technology presents challenges not only to wafer processing but also to quality and reliability testing and assembling of the integrated circuits.
Compared to the previous generations of silicone dioxide dielectric layers, the low-K layer is characterized by poorer mechanical properties. It can be either softer than a silicone oxide layer or more brittle than the silicone oxide layer. Accordingly, the low-K film is more easily damaged or deformed by a probe that is used to electrically test the integrated circuit. The probes contact integrated circuit test pads and imprint a so-called probe mark on these pads.
The probe marks can affect the functionality of the integrated circuit. For example, deep probe marks can expose a layer that should be buried under the pad. Probe marks can cause shorts or disconnections and effect wire bonding integrity.
Probe marks are relatively shallow and rough and their shape is hard to evaluate. Highly accurate probe mark depth measurements such as atomic force microscope based measurements and focused ion beam cross sectioning based measurements are very costly, very slow and are depending on human interpretation.
Measuring probe mark depth by conventional chromatic confocal systems is very slow and its axial accuracy is limited especially when the chromatic confocal systems are located few centimeters from the wafer.
There is a need to provide a highly accurate high throughput probe mark evaluation method and system.